The present invention relates to a system for generating a mask pattern for a mask register (MR) in a vector data processing apparatus, for use in a supercomputer, having a calculational mask function by means of the mask register.
In recent years, with the increased use of vector processors, that is, supercomputors, the vector processor have been used in the fields of fast Fourier transformation, such as in radio astronomy or image processing. A performance evaluation of the application program and other programs is necessary.
As a result, the problems in vector data processing are becoming known. For example, it is now known that the generating capability of a mask pattern of the so-called mask calculation by dint of the mask operand, conspicuously enhances the processing capability of the vector processor. Thus the development of a system for generating the mask pattern with a high efficiency has long been desired.
A prior art mask pattern generation system will be described with reference to FIG. 2.
In the prior art, a mask pattern generation instruction (hereinafter, referred to as VGM) can not make a mask pattern such that only a specified element of a mak register is "1" or "0" and the other elements are all "0" or all "1".
That is, when the VGM instruction is executed, the value at the R2 portion of an instruction (hereinafter, referred to as R2I) is input to an adder 3, after a complement representation of 1 is obtained by a complement number generating circuit (COMP) 1.
A definite number, for example,"1" from a constant circuit (CNST) 2 and a complement of 1 in the above-mentioned R2I are added, so a definite number "1" is subtracted from said R2I. Then, the output of a decoder (VGM) 4 and a modifier (MI) designated by said VGM instruction execute an exclusive OR operation in an exclusive OR circuit XOR, to store the result in the head element of mask registor which is assigned by the VGM instruction.
That is to say, if the above-described modifier (MI) is "0", "000 - - - 0" is stored, whereas, if the modifier (MI) is "1", the system functions so that "111 - - - 1" is stored.
When the above-described subtraction result is 37 0", the output of said decoder (VGM) 4 is "1", and "1" or "0" is stored in the element of the mask register assigned at that time, according to the value of the modifier (MI).
Therefore, the output of the decoder (VGM) 4 is "0", and functions so that "000 - - - 0" or "111 - - - 1" is stored into the mask register for the vector length (VL).
The example of a mask pattern so generated is shown in FIGS. 3A and 3B.
Therefore, in order to generate a mask pattern which is necessary to the vector operation as shown in FIGS. 4A and 4B, first, a plurality of vector instructions and scalar instructions are necessary, and second, a mask pattern is stored in the memory in advance and must be loaded into the mask register from said memory every time it is needed.
For example, when such a pattern is generated by the aforementioned first vector instruction, the following object program is created and executed.
______________________________________ (i) L GR1 = 1 (ii) L GR2 = i (iii) L GR3 = j (iv) VGS VR1, GR1 (v) VCS* MR1, GR2, VR1 (vi) VCS* MR2, GR3, VR1 (vii) VNM MR3, MR2, MR1 ______________________________________
In the above-described program, the first three load instructions (i) to (iii), GR1=1, GR2=i, and GR3=j are set to a respective general-purpose register GR.
The next vector generation series (VGS) instruction creates an arithmetic progression which represents the content (in this example "1") of the general-purpose register (GR1) inthe vector register (VR1). That is, in this example, a progression EQU VR1: 1, 2, 3, 4, - - - VL
is stored therein.
In the following vector comparison scalar (VCS*) instruction (v), a content of GR2 and VR1, which was created by the above-mentioned instruction, is compared and then, if EQU GR2&lt;VR1,
"1" is introduced into a respective element of a corresponding mask register. This is expressed as follows: EQU MR1; 000 - - - 01111 - - - 1 (From the i-th element converted to "1")
Similarly, in the vector comparison scalar (VCS*) instruction (vi), a content of GR3 and VR1, which is created by the above-mentioned instruction, is compared and then, if EQU GR3&gt;VR1,
"1" is introduced into a respective element of the corresponding mask register. This is expressed as follows: EQU MR2: 111 - - - 1000 - - - 0 (From the j-th element, converted to "0")
In the last vector and mask (VNM) instruction (vii), taking the logical product of a mask register MR1 and MR2, the product is stored in a mask register (MR3).
As a result, the following bit pattern is obtained in a mask register (MR3). That is, EQU MR3; 000 - - - 0111 - - - 1000 - - - 0 (From the i-th element to the j-th minus 1 element, equal to "1")
Therefore, in the case where a mask pattern in which a plurality of "1"'s or "0"'s are placed between "0" or "1", is generated in accordance with a vector instruction, there is a problem that the overhead is increased.
According to the above-mentioned second point, since only the mask pattern stored in a memory in advance can be used, there is a problem that the desired mask pattern can not be obtained each time the program is run.